Jae Hoon Shim

Orcid: 0009-0009-4292-4539

According to our database1, Jae Hoon Shim authored at least 17 papers between 2001 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
An Output-Capacitor-Free NMOS Digital LDO Using Gate Driving Strength Modulation and Droop Detector.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

An Output-Capacitor-Free Adaptive-Frequency Digital LDO with a 420-mA Load Current and a Fast Settling Time.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2021
A Zero-Crossing-Based Integrator with Bidirectional Two-Phase Charging and Selective-Reset Operations for ΔΣ ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Lossless Image Compression Based on Image Decomposition and Progressive Prediction Using Convolutional Neural Networks.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2021

Network Intrusion Detection with Improved Feature Representation.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2021

2018
Modified adaptive support weight and disparity search range estimation schemes for stereo matching processors.
J. Supercomput., 2018

3D die-stacked DRAM thermal management via task allocation and core pipeline control.
IEICE Electron. Express, 2018

A Low-Power 2nd-Order Delta-Sigma ADC with an Inverter-Based Zero-Crossing Detector.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors.
Sensors, 2017

2010
Charge Pump circuit with wide range digital leakage current mismatch compensator.
IEICE Electron. Express, 2010

2006
A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector.
IEEE J. Solid State Circuits, 2006

A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
Hybrid ΣΔ modulators with adaptive calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Correction to "A Third-Order$Sigma Delta $Modulator in 0.18-$muhboxm$CMOS With Calibrated Mixed-Mode Integrators".
IEEE J. Solid State Circuits, 2005

A third-order ΣΔ modulator in 0.18-μm CMOS with calibrated mixed-mode integrators.
IEEE J. Solid State Circuits, 2005

2003
A hybrid delta-sigma modulator with adaptive calibration.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2001
A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique.
IEEE J. Solid State Circuits, 2001


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