Sanjay Deshpande
Orcid: 0009-0005-0938-9547
According to our database1,
Sanjay Deshpande
authored at least 17 papers
between 2011 and 2025.
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Bibliography
2025
SPHINCSLET: An Area-Efficient Accelerator for the Full SPHINCS+ Digital Signature Algorithm.
IACR Cryptol. ePrint Arch., 2025
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025
2024
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2024
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024
2023
CoRR, 2023
CoRR, 2023
Proceedings of the Selected Areas in Cryptography - SAC 2023, 2023
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023
2022
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
IACR Cryptol. ePrint Arch., 2022
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022
2021
Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
2017
Analysis and Inner-Round Pipelined Implementation of Selected Parallelizable CAESAR Competition Candidates.
Proceedings of the Euromicro Conference on Digital System Design, 2017
2011
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011