Sanjay Ramnath

According to our database, Sanjay Ramnath authored at least 5 papers between 2002 and 2007.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2007

DFT MAX and Power.

Rohit Kapur, T. Finklea, Felix Ng, Anshuman Chandra, Sanjay Ramnath, Peter Wohl, Thomas W. Williams, Ashok Anbalan, Sandeep S. Kulkarni, Tammy Fernandes, Pramod Notiyath, Rajesh Uppuluri

J. Low Power Electron., 2007

Minimizing the Impact of Scan Compression.

Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Fully X-tolerant combinational scan compression.

Peter Wohl, John A. Waicukauski, Sanjay Ramnath

Proceedings of the 2007 IEEE International Test Conference, 2007

2005

Power and Design for Test: A Design Automation Perspective.

Aurelia De Colle, Sanjay Ramnath, Mokhtar Hirech, Subramanian Chebiyam

J. Low Power Electron., 2005

2002

Test-model based hierarchical DFT synthesis.

Sanjay Ramnath, Frederic Neuveux, Mokhtar Hirech, Felix Ng

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002