Mokhtar Hirech

According to our database, Mokhtar Hirech authored at least 7 papers between 1994 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

Test cost and test power conflicts: EDA perspective.

Mokhtar Hirech

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

2008

Test Strategies for Low-Power Devices.

C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen

J. Low Power Electron., 2008

2005

Power and Design for Test: A Design Automation Perspective.

Aurelia De Colle, Sanjay Ramnath, Mokhtar Hirech, Subramanian Chebiyam

J. Low Power Electron., 2005

2002

Test-model based hierarchical DFT synthesis.

Sanjay Ramnath, Frederic Neuveux, Mokhtar Hirech, Felix Ng

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

1998

A new approach to scan chain reordering using physical design information.

Mokhtar Hirech, James Beausang, Xinli Gu

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1994

A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking.

Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Application of a redefinable symbolic simulation technique in VLSI testability design rules checking.

Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan

Proceedings of the Proceedings 27th Annual Simulation Symposium, 1994