Saranya Karunamurthi

According to our database, Saranya Karunamurthi authored at least 8 papers between 2019 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

ASIC design of trimmed weighted mean filter for image processing applications: An analog implementation.

K. N. Vijeyakumar, P. Vanjipriya, Saranya Karunamurthi, Rahul Suresh Shanmugasundharam

Integr., 2026

2025

Area-efficient low-power image watermarking architecture using faithful approximation and reversible logic.

Silambarasan D., Vijeyakumar Krishnasamy Natarajan, Saranya Karunamurthi

Multim. Tools Appl., May, 2025

Design and analysis of faithful parallel mean filter using approximate adders and 4:2 compressors for low-power VLSI architectures.

K. N. Vijeyakumar, Talluri Vineel Jessy, Saranya Karunamurthi, B. Naresh Kumar Reddy

Integr., 2025

2023

Design of area, energy and security optimized reversible architectures for digital image cryptography.

Saranya Karunamurthi, Vijeyakumar Krishnasamy Natarajan

Circuits Syst. Signal Process., 2023

2022

A New Approximate 4-2 Compressor using Merged Sum and Carry.

Chinthalgiri Jyothi, Saranya Karunamurthi, Bhaskara Rao Jammu, Sreehari Veeramachaneni, Sk. Noor Mahammad

J. Electron. Test., 2022

2021

A Low Area FPGA Implementation of Reversible Gate Encryption with Heterogeneous Key Generation.

Saranya Karunamurthi, Vijeyakumar Krishnasamy Natarajan

Circuits Syst. Signal Process., 2021

A Novel n-Decimal Reversible Radix Binary-Coded Decimal Multiplier Using Radix Encoding Scheme.

Saranya Karunamurthi, Vijeyakumar Krishnasamy Natarajan

Circuits Syst. Signal Process., 2021

2019

VLSI implementation of reversible logic gates cryptography with LFSR key.

Saranya Karunamurthi, Vijeyakumar Krishnasamy Natarajan

Microprocess. Microsystems, 2019