Satyaprakash Pareek

According to our database, Satyaprakash Pareek authored at least 4 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

XVDPU: A High-Performance CNN Accelerator on the Versal Platform Powered by the AI Engine.

Xijie Jia, Yu Zhang, Guangdong Liu, Xinlin Yang, Tianyu Zhang, Jia Zheng, Dongdong Xu, Zhuohuan Liu, Mengke Liu, Xiaoyang Yan, Hong Wang, Rongzhang Zheng, Li Wang, Dong Li, Satyaprakash Pareek, Jian Weng, Lu Tian, Dongliang Xie, Hong Luo, Yi Shan

ACM Trans. Reconfigurable Technol. Syst., June, 2024

AMD XDNA NPU in Ryzen AI Processors.

Alejandro Rico, Satyaprakash Pareek, Javier Cabezas, David Clarke, Baris Özgül, Francisco Barat, Yao Fu, Stephan Münz, Dylan Stuart, Patrick Schlangen, Pedro Duarte, Sneha Date, Indrani Paul, Jian Weng, Sonal Santan, Vinod Kathail, Ashish Sirasao, Juanjo Noguera

IEEE Micro, 2024

Parallelization Strategies for DLRM Embedding Bag Operator on AMD CPUs.

Krishnakumar Nair, Avinash-Chandra Pandey, Siddappa Karabannavar, Meena Arunachalam, John Kalamatianos, Varun Agrawal, Saurabh Gupta, Ashish Sirasao, Elliott Delaye, Steven K. Reinhardt, Rajesh Vivekanandham, Ralph Wittig, Vinod Kathail, Padmini Gopalakrishnan, Satyaprakash Pareek, Rishabh Jain, Mahmut Taylan Kandemir, Jun-Liang Lin, Gulsum Gudukbay Akbulut, Chita R. Das

IEEE Micro, 2024

2022

XVDPU: A High Performance CNN Accelerator on the Versal Platform Powered by the AI Engine.

Xijie Jia, Yu Zhang, Guangdong Liu, Xinlin Yang, Tianyu Zhang, Jia Zheng, Dongdong Xu, Hong Wang, Rongzhang Zheng, Satyaprakash Pareek, Lu Tian, Dongliang Xie, Hong Luo, Yi Shan

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022