Alejandro Rico

According to our database1, Alejandro Rico
  • authored at least 23 papers between 2009 and 2017.
  • has a "Dijkstra number"2 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2017
Task Scheduling Techniques for Asymmetric Multi-Core Systems.
IEEE Trans. Parallel Distrib. Syst., 2017

The ARM Scalable Vector Extension.
IEEE Micro, 2017

Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors.
International Journal of Parallel Programming, 2017

Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

ARM HPC Ecosystem and the Reemergence of Vectors: Invited Paper.
Proceedings of the Computing Frontiers Conference, 2017

2016

MUSA: a multi-level simulation approach for next-generation HPC machines.
Proceedings of the International Conference for High Performance Computing, 2016

TaskPoint: Sampled simulation of task-based programs.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

Rebalancing the core front-end through HPC code analysis.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

Evaluating the effect of last-level cache sharing on integrated GPU-CPU systems with heterogeneous applications.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Experiences in speeding up computer vision applications on mobile computing platforms.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Criticality-Aware Dynamic Task Scheduling for Heterogeneous Architectures.
Proceedings of the 29th ACM on International Conference on Supercomputing, 2015

2014
Tibidabo: Making the case for an ARM-based HPC system.
Future Generation Comp. Syst., 2014

Evaluating Execution Time Predictability of Task-Based Programs on Multi-Core Processors.
Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014

2013
Trace filtering of multithreaded applications for CMP memory simulation.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Experiences with mobile processors for energy efficient HPC.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
On the simulation of large-scale architectures using multiple application abstraction levels.
TACO, 2012

2011
Trace-driven simulation of multithreaded applications.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

2010
Interleaving granularity on high bandwidth memory architecture for CMPs.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Task Superscalar: An Out-of-Order Task Pipeline.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Performance and power evaluation of an in-line accelerator.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
Available task-level parallelism on the Cell BE.
Scientific Programming, 2009


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