John Kalamatianos

Affiliations:
  • Northeastern University, Boston, USA


According to our database1, John Kalamatianos authored at least 23 papers between 1995 and 2023.

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Bibliography

2023

Temperature-Aware Sizing of Multi-Chip Module Accelerators for Multi-DNN Workloads.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Cloak: tolerating non-volatile cache read latency.
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022

2021
A Method for Hiding the Increased Non-Volatile Cache Read Latency.
CoRR, 2021

2020
Improving the Utilization of Micro-operation Caches in x86 Processors.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

2019
Assessing the Effects of Low Voltage in Branch Prediction Units.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Killi: Runtime Fault Classification to Deploy Low Voltage Caches without MBIST.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2018
Analysis and Characterization of Ultra Low Power Branch Predictors.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Lost in Abstraction: Pitfalls of Analyzing GPUs at the Intermediate Language Level.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
Compiler Techniques to Reduce the Synchronization Overhead of GPU Redundant Multithreading.
Proceedings of the 54th Annual Design Automation Conference, 2017

On Characterizing Near-Threshold SRAM Failures in FinFET Technology.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Faults in data prefetchers: Performance degradation and variability.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

2013
Measuring the performance impact of permanent faults in modern microprocessor architectures.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Assessing the impact of hard faults in performance components of modern microprocessors.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2004
A Study of Errant Pipeline Flushes Caused by Value Misspeculation.
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004

2000
High-Speed Parallel-Prefix Modulo 2n-1 Adders.
IEEE Trans. Computers, 2000

Accurate simulation and evaluation of code reordering.
Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software, 2000

1999
Analysis of Temporal-Based Program Behavior for Improved Instruction Cache Performance.
IEEE Trans. Computers, 1999

Improving the accuracy of indirect branch prediction via branch classification.
SIGARCH Comput. Archit. News, 1999

Indirect Branch Prediction Using Data Compression Techniques.
J. Instr. Level Parallelism, 1999

1998
Predicting Indirect Branches via Data Compression.
Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998

Temporal-Based Procedure Reordering for Improved Instruction Cache Performance.
Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998

1995
Parallel computation of higher order moments on the MasPar-1 machine.
Proceedings of the 1995 International Conference on Acoustics, 1995


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