Vinod Kathail

According to our database, Vinod Kathail authored at least 23 papers between 1990 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Xilinx Vitis Unified Software Platform.

Vinod Kathail

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2016

A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform.

Sagheer Ahmad, Vamsi Boppana, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig

IEEE Micro, 2016

SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC.

Vinod Kathail, James Hwang, Welson Sun, Yogesh Chobe, Tom Shui, Jorge Carrillo

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

UltraScale+ MPSoC and FPGA families.

Vamsi Boppana, Sagheer Ahmad, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2010

Programming high performance signal processing systems in high level languages.

Kees A. Vissers, Devada Varma, Vinod Kathail, Jeff Bier, Don MacMillen, Joseph R. Cavallaro

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2008

Architecture Exploration for Low Power Design.

Vinod Kathail, Tom Miller

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007

Tutorial T8A: Automated Application Engine Synthesis from C Algorithms.

Vinod Kathail, Shail Aditya, Craig Gleason, Nagesh Chatekar

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2002

PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators.

Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman

J. VLSI Signal Process., 2002

PICO: Automatically Designing Custom Computers.

Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman

Computer, 2002

2001

Compiling for EPIC architectures.

Vinod Kathail, Michael S. Schlansker, B. Ramakrishna Rau

Proc. IEEE, 2001

2000

High-Level Synthesis of Nonprogrammable Hardware Accelerators.

Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider

Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999

Machine-Description Driven Compilers for EPIC and VLIW Processors.

B. Ramakrishna Rau, Vinod Kathail, Shail Aditya

Des. Autom. Embed. Syst., 1999

Fine Grained Register Allocation for EPIC Processors With Predication.

Hansoo Kim, Vinod Kathail, Kanchi Gopinath, Bhagirath Narahari

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

Register allocation in hyper-block for EPIC processors.

Hansoo Kim, Kanchi Gopinath, Vinod Kathail

Proceedings of the Parallel Computing: Fundamentals & Applications, 1999

Automatic Architectural Synthesis of VLIW and EPIC Processors.

Shail Aditya, B. Ramakrishna Rau, Vinod Kathail

Proceedings of the 12th International Symposium on System Synthesis, 1999

1998

Meld Scheduling: A Technique for Relaxing Scheduling Constraints.

Santosh G. Abraham, Vinod Kathail, Brian L. Deitrich

Int. J. Parallel Program., 1998

1997

Techniques for critical path reduction of scalar programs.

Michael S. Schlansker, Vinod Kathail

Int. J. Parallel Program., 1997

1996

Parallelization of Control Recurrences for ILP Processors.

Michael S. Schlansker, Vinod Kathail, Sadun Anik

Int. J. Parallel Program., 1996

Meld Scheduling: Relaxing Scheduling Constraints Across Region Boundaries.

Santosh G. Abraham, Vinod Kathail, Brian L. Deitrich

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

1995

Critical path reduction for scalar programs.

Michael S. Schlansker, Vinod Kathail

Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

1994

Height reduction of control recurrences for ILP processors.

Michael S. Schlansker, Vinod Kathail, Sadun Anik

Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

1993

Acceleration of First and Higher Order Recurrences on Processors with Instruction Level Parallelism.

Michael S. Schlansker, Vinod Kathail

Proceedings of the Languages and Compilers for Parallel Computing, 1993

1990

Optimal interpreters for lambda-calculus based functional languages.

Vinod Kathail

PhD thesis, 1990