Francisco Barat

According to our database1, Francisco Barat authored at least 15 papers between 2000 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




An Ultra Low Energy Biomedical Signal Processing System Operating at Near-Threshold.
IEEE Trans. Biomed. Circuits and Systems, 2011

A voltage-scalable biomedical signal processor running ECG using 13pJ/cycle at 1MHz and 0.4V.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors.
IEEE Trans. Computers, 2005

Instruction buffering exploration for low energy embedded processors.
J. Embedded Computing, 2005

L0 buffer energy optimization through scheduling and exploration.
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

Design Style Case Study for Embedded Multi Media Compute Nodes.
Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 2004

L0 Cluster Synthesis and Operation Shuffling.
Proceedings of the Integrated Circuit and System Design, 2004

Instruction buffering exploration for low energy VLIWs with instruction clusters.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Low Power Coarse-Grained Reconfigurable Instruction Set Processor.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Reconfigurable Instruction Set Processors from a Hardware/Software Perspective.
IEEE Trans. Software Eng., 2002

Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Bridging the Educational Gap in Embedded Systems Curricula: Developing an E-commerce Audio Streaming System.
Proceedings of the 9th IEEE International Conference on Engineering of Computer-Based Systems (ECBS 2002), 2002

CRISP: A Template for Reconfigurable Instruction Set Processors.
Proceedings of the Field-Programmable Logic and Applications, 2001

Reconfigurable Instruction Set Processors: A Survey.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000