Juanjo Noguera

According to our database1, Juanjo Noguera authored at least 37 papers between 1999 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Xilinx First 7nm Device: Versal AI Core (VC1902).
Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

2015
Coarse-Grain Performance Estimator for Heterogeneous Parallel Computing Architectures like Zynq All-Programmable SoC.
CoRR, 2015

2014
OmpSs@Zynq all-programmable SoC ecosystem.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013
Software-programmable digital pre-distortion on the Zynq SoC.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Heterogeneous tasking on SMP/FPGA SoCs: The case of OmpSs and the Zynq.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

2011
High-Level Synthesis for FPGAs: From Prototyping to Deployment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A Model-Based Approach to Cognitive Radio Design.
IEEE J. Sel. Areas Commun., 2011

Embedded Systems Start-Up under Timing Constraints on Modern FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools.
Proceedings of the Design, Automation and Test in Europe, 2011

Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures.
ACM Trans. Reconfigurable Technol. Syst., 2010

Iris: an architecture for cognitive radio networking testbeds.
IEEE Commun. Mag., 2010

FPGA Startup Through Sequential Partial and Dynamic Reconfiguration.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Multi-platform demonstrations using the Iris architecture for cognitive radio network testbeds.
Proceedings of the 5th International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2010

2009
Development Framework for Implementing FPGA-Based Cognitive Network Nodes.
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

Generic Software Framework for Adaptive Applications on FPGAs.
Proceedings of the FCCM 2009, 2009

2008
Towards Novel Approaches in Design Automation for FPGA Power Optimization.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007
Power Reduction in Network Equipment through Adaptive Partial Reconfiguration.
Proceedings of the FPL 2007, 2007

Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures.
Proceedings of the 44th Design Automation Conference, 2007

2006
System-level power-performance tradeoffs for reconfigurable computing.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Minimizing peak power for application chains on architectures with partial dynamic reconfiguration.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Software-friendly HW/SW co-simulation: an industrial case study.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005
Performance and Energy Analysis of Task-Level Graph Transformation Techniques for Dynamically Reconfigurable Architectures.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Improved Microarchitecture Support for Dynamic Task Scheduling on Reconfigurable Architectures.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

2004
Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling.
ACM Trans. Embed. Comput. Syst., 2004

Power-performance trade-offs for reconfigurable computing.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003
System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures.
Proceedings of the International Conference on Compilers, 2003

2002
HW/SW codesign techniques for dynamically reconfigurable architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
A HW/SW partitioning algorithm for dynamically reconfigurable architectures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Run-Time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Modelling and Performance Evaluation of a National Scale Switchless Based Network.
Proceedings of the Next Generation Networks, 2000

Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers.
Proceedings of the Field-Programmable Logic and Applications, 2000

1999
A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Reconfigurable Computing: An Innovative Solution for Multimedia and Telecommunication Networks Simulation.
Proceedings of the 25th EUROMICRO '99 Conference, 1999


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