Saurabh Dhiman

Orcid: 0000-0003-4725-6620

According to our database1, Saurabh Dhiman authored at least 6 papers between 2019 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Late Breaking Results - A Systematic Vulnerability Analysis of MRAM-Based Compute-in-Memory against Side-Channel Attacks.
Proceedings of the 44th IEEE VLSI Test Symposium, 2026

2024
Corrigendum to "On minimizing charge injection error using multi-dummy switches with enhanced linearity" [Integration volume 97 (2024) 102175].
Integr., 2024

On Minimizing Charge Injection Error Using Multi-Dummy Switches With Enhanced Linearity.
Integr., 2024

A 12.7 Bit Accurate and 5.3nJ·µV<sup>2</sup>·ns Comparator with Dynamic-cum-Body Bias Technique in SOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2020
Design and Analysis of a Low PSIJ, Energy Efficient Bootstrapped Driver for Space Application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Energy Efficient Bootstrapped Driver for a Particle Detector in 180 nm SOI Technology.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019


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