Farshad Firouzi

According to our database1, Farshad Firouzi authored at least 36 papers between 2010 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Keynote Paper: From EDA to IoT eHealth: Promises, Challenges, and Solutions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Internet-of-Things and big data for smarter healthcare: From device to architecture, applications and analytics.
Future Generation Comp. Syst., 2018

Towards fog-driven IoT eHealth: Promises and challenges of IoT in medicine and healthcare.
Future Generation Comp. Syst., 2018

2017
Guest Editorial: Alternative Computing and Machine Learning for Internet of Things.
IEEE Trans. VLSI Syst., 2017

2016
On-Chip Droop-Induced Circuit Delay Prediction Based on Support-Vector Machines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

2015
Resilient Design for Process and Runtime Variations.
PhD thesis, 2015

Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection.
ACM Trans. Design Autom. Electr. Syst., 2015

Extending standard cell library for aging mitigation.
IET Computers & Digital Techniques, 2015

Deadspace-aware Power/Ground TSV planning in 3D floorplanning.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Re-using BIST for circuit aging monitoring.
Proceedings of the 20th IEEE European Test Symposium, 2015

On-line prediction of NBTI-induced aging rates.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Stress-aware P/G TSV planning in 3D-ICs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
On-chip voltage-droop prediction using support-vector machines.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Chip Health Monitoring Using Machine Learning.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

P/G TSV planning for IR-drop reduction in 3D-ICs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Aging-aware standard cell library design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Adaptive Mitigation of Parameter Variations.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Power-Aware Minimum NBTI Vector Selection Using a Linear Programming Approach.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Negative Bias Temperature Instability-Aware Instruction Scheduling: A Cross-Layer Approach.
J. Low Power Electronics, 2013

Chip-level modeling and analysis of electrical masking of soft errors.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Representative critical-path selection for aging-induced delay monitoring.
Proceedings of the 2013 IEEE International Test Conference, 2013

Aging-aware timing analysis considering combined effects of NBTI and PBTI.
Proceedings of the International Symposium on Quality Electronic Design, 2013

A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing.
Proceedings of the 18th IEEE European Test Symposium, 2013

Instruction-set extension under process variation and aging effects.
Proceedings of the Design, Automation and Test in Europe, 2013

Incorporating the impacts of workload-dependent runtime variations into timing analysis.
Proceedings of the Design, Automation and Test in Europe, 2013

Statistical analysis of BTI in the presence of process-induced voltage and temperature variations.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Adaptive fault-tolerant DVFS with dynamic online AVF prediction.
Microelectronics Reliability, 2012

Input and transistor reordering for NBTI and HCI reduction in complex CMOS gates.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

NBTI mitigation by optimized NOP assignment and insertion.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
An accurate model for soft error rate estimation considering dynamic voltage and frequency scaling effects.
Microelectronics Reliability, 2011

Modeling and estimation of power supply noise using linear programming.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A linear programming approach for minimum NBTI vector selection.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Dynamic Soft Error Hardening via Joint Body Biasing and Dynamic Voltage Scaling.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Reliability-Aware Dynamic Voltage and Frequency Scaling.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Instruction reliability analysis for embedded processors.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010


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