Rajendra Bishnoi
Orcid: 0000-0002-1590-0365
According to our database1,
Rajendra Bishnoi
authored at least 82 papers
between 2014 and 2024.
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Bibliography
2024
Reliable and Energy-Efficient Diabetic Retinopathy Screening Using Memristor-Based Neural Networks.
IEEE Access, 2024
Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024
Dynamic Detection and Mitigation of Read-disturb for Accurate Memristor-based Neural Networks.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
2023
IEEE Trans. Emerg. Top. Comput. Intell., February, 2023
IEEE Trans. Biomed. Circuits Syst., February, 2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Proceedings of the International Conference on Microelectronics, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Read-disturb Detection Methodology for RRAM-based Computation-in-Memory Architecture.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
A 115.1 TOPS/W, 12.1 TOPS/mm<sup>2</sup> Computation-in-Memory using Ring-Oscillator based ADC for Edge AI.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Neuromorph. Comput. Eng., 2022
A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs.
ACM J. Emerg. Technol. Comput. Syst., 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
SRIF: Scalable and Reliable Integrate and Fire Circuit ADC for Memristor-Based CIM Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Proc. IEEE, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
A Compact Low-Voltage True Random Number Generator Based on Inkjet Printing Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
ACM J. Emerg. Technol. Comput. Syst., 2020
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Proceedings of the IEEE European Test Symposium, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Tolerating Retention Failures in Neuromorphic Fabric based on Emerging Resistive Memories.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Fast and Reliable STT-MRAM Using Nonuniform and Adaptive Error Detecting and Correcting Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2019
A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Compiler-Assisted and Profiling-Based Analysis for Fast and Efficient STT-MRAM On-Chip Cache Design.
ACM Trans. Design Autom. Electr. Syst., 2019
A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
Inkjet-Printed EGFET-Based Physical Unclonable Function - Design, Evaluation, and Fabrication.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the IEEE International Test Conference, 2018
Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM.
Proceedings of the IEEE International Test Conference, 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Design and evaluation of physical unclonable function for inorganic printed electronics.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing.
IEEE Trans. Multi Scale Comput. Syst., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
A cross-layer analysis of Soft Error, aging and process variation in Near Threshold Computing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Non-Volatile Non-Shadow flip-flop using Spin Orbit Torque for efficient normally-off computing.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
2014
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014