Rajendra Bishnoi

According to our database1, Rajendra Bishnoi authored at least 54 papers between 2014 and 2020.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
A Novel Printed-Lookup-Table-Based Programmable Printed Digital Circuit.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A Compact Low-Voltage True Random Number Generator Based on Inkjet Printing Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Secure STT-MRAM Bit-Cell Design Resilient to Differential Power Analysis Attacks.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Approximate Spintronic Memories.
ACM J. Emerg. Technol. Comput. Syst., 2020

Crossover-aware Placement and Routing for Inkjet Printed Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2020

Mitigating Read Failures in STT-MRAM.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Testing Scouting Logic-Based Computation-in-Memory Architectures.
Proceedings of the IEEE European Test Symposium, 2020

A Universal Spintronic Technology based on Multifunctional Standardized Stack.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Dynamic Faults based Hardware Trojan Design in STT-MRAM.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Tolerating Retention Failures in Neuromorphic Fabric based on Emerging Resistive Memories.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Fast and Reliable STT-MRAM Using Nonuniform and Adaptive Error Detecting and Correcting Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A Spintronics Memory PUF for Resilience Against Cloning Counterfeit.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Compiler-Assisted and Profiling-Based Analysis for Fast and Efficient STT-MRAM On-Chip Cache Design.
ACM Trans. Design Autom. Electr. Syst., 2019

A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Variation-aware Fault Modeling and Test Generation for STT-MRAM.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Predictive Modeling and Design Automation of Inorganic Printed Electronics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Inkjet-Printed True Random Number Generator based on Additive Resistor Tuning.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Reliable in-memory neuromorphic computing using spintronics.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Inkjet-Printed EGFET-Based Physical Unclonable Function - Design, Evaluation, and Fabrication.
IEEE Trans. Very Large Scale Integr. Syst., 2018

VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications.
Proceedings of the IEEE International Test Conference, 2018

Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM.
Proceedings of the IEEE International Test Conference, 2018

Reliable memory PUF design for low-power applications.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Design and evaluation of physical unclonable function for inorganic printed electronics.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Using multifunctional standardized stack as universal spintronic technology for IoT.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

A cross-layer adaptive approach for performance and power optimization in STT-MRAM.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Parametric failure modeling and yield analysis for STT-MRAM.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Multi-bit non-volatile spintronic flip-flop.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Spintronic normally-off heterogeneous system-on-chip design.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Leveraging Systematic Unidirectional Error-Detecting Codes for fast STT-MRAM cache.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Architecting SOT-RAM Based GPU Register File.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Exploiting STT-MRAM for approximate computing.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Opportunistic write for fast and reliable STT-MRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

VAET-STT: A variation aware estimator tool for STT-MRAM based memories.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Self-Timed Read and Write Operations in STT-MRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing.
IEEE Trans. Multi Scale Comput. Syst., 2016

Layout-Based Modeling and Mitigation of Multiple Event Transients.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

A cross-layer analysis of Soft Error, aging and process variation in Near Threshold Computing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Fault Tolerant Non-Volatile spintronic flip-flop.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Non-Volatile Non-Shadow flip-flop using Spin Orbit Torque for efficient normally-off computing.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014
Read disturb fault detection in STT-MRAM.
Proceedings of the 2014 International Test Conference, 2014

Avoiding unnecessary write operations in STT-MRAM for low power implementation.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Architectural aspects in design and analysis of SOT-based memories.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014


  Loading...