Saurabh Khandelwal

According to our database, Saurabh Khandelwal authored at least 12 papers between 2012 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2022

Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability.

Anu Bala, Saurabh Khandelwal, Abusaleh M. Jabir, Marco Ottavi

Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

2021

A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations.

Saurabh Khandelwal, Marco Ottavi, Eugenio Martinelli, Abusaleh M. Jabir

Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Reliability Assessment of Memristor based Gas Sensor Array.

Vishal Gupta, Giulio Panunzi, Saurabh Khandelwal, Eugenio Martinelli, Abusaleh M. Jabir, Marco Ottavi

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020

Yield Estimation of a Memristive Sensor Array.

Vishal Gupta, Saurabh Khandelwal, Giulio Panunzi, Eugenio Martinelli, Said Hamdioui, Abusaleh M. Jabir, Marco Ottavi

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

A Modelling Attack Resistant Low Overhead Memristive Physical Unclonable Function.

Xiaohan Yang, Saurabh Khandelwal, Aiqi Jiang, Abusaleh M. Jabir

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations.

Vishal Gupta, Danilo Pellegrini, Saurabh Khandelwal, Abusaleh M. Jabir, Shahar Kvatinsky, Eugenio Martinelli, Corrado Di Natale, Marco Ottavi

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019

The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors.

Marco Ottavi, Vishal Gupta, Saurabh Khandelwal, Shahar Kvatinsky, Jimson Mathew, Eugenio Martinelli, Abusaleh M. Jabir

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Fault Modeling and Simulation of Memristor based Gas Sensors.

Saurabh Khandelwal, Anu Bala, Vishal Gupta, Marco Ottavi, Eugenio Martinelli, Abusaleh M. Jabir

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2018

45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control.

Vishal Gupta, Saurabh Khandelwal, Jimson Mathew, Marco Ottavi

Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

2016

FinFET Design Considerations Based on Schmitt Trigger with Slew Rate and Gain-Bandwidth Product Analysis.

Pawan Sharma, Saurabh Khandelwal, Shyam Akashe

Wirel. Pers. Commun., 2016

2015

Modeling and Optimization of Nano-Scale Sensing Shorted Gate FinFET D Flip-Flop Using AVL.

Pooja Joshi, Saurabh Khandelwal, Shyam Akashe

J. Low Power Electron., 2015

2012

Analyzing Different Mode FinFET Based Memory cell at different power supply for Leakage Reduction.

Sushil Bhushan, Saurabh Khandelwal, Balwinder Raj

Proceedings of Seventh International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2012), 2012