Abusaleh M. Jabir

According to our database, Abusaleh M. Jabir authored at least 49 papers between 2001 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability.

Anu Bala, Saurabh Khandelwal, Abusaleh M. Jabir, Marco Ottavi

Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

2021

A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations.

Saurabh Khandelwal, Marco Ottavi, Eugenio Martinelli, Abusaleh M. Jabir

Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Reliability Assessment of Memristor based Gas Sensor Array.

Vishal Gupta, Giulio Panunzi, Saurabh Khandelwal, Eugenio Martinelli, Abusaleh M. Jabir, Marco Ottavi

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020

Yield Estimation of a Memristive Sensor Array.

Vishal Gupta, Saurabh Khandelwal, Giulio Panunzi, Eugenio Martinelli, Said Hamdioui, Abusaleh M. Jabir, Marco Ottavi

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

A Modelling Attack Resistant Low Overhead Memristive Physical Unclonable Function.

Xiaohan Yang, Saurabh Khandelwal, Aiqi Jiang, Abusaleh M. Jabir

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations.

Vishal Gupta, Danilo Pellegrini, Saurabh Khandelwal, Abusaleh M. Jabir, Shahar Kvatinsky, Eugenio Martinelli, Corrado Di Natale, Marco Ottavi

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019

Efficient and Low Overhead Memristive Activation Circuit for Deep Learning Neural Networks.

Anu Bala, Xiaohan Yang, Adedotun Adeyemo, Abusaleh M. Jabir

J. Low Power Electron., 2019

Novel techniques for memristive multifunction logic design.

Xiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir

Integr., 2019

The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors.

Marco Ottavi, Vishal Gupta, Saurabh Khandelwal, Shahar Kvatinsky, Jimson Mathew, Eugenio Martinelli, Abusaleh M. Jabir

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Fault Modeling and Simulation of Memristor based Gas Sensors.

Saurabh Khandelwal, Anu Bala, Vishal Gupta, Marco Ottavi, Eugenio Martinelli, Abusaleh M. Jabir

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2018

A Memristive Activation Circuit for Deep Learning Neural Networks.

Anu Bala, Xiaohan Yang, Adedotun Adeyemo, Abusaleh M. Jabir

Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

2017

Minimising Impact of Wire Resistance in Low-Power Crossbar Array Write Scheme.

Adedotun Adeyemo, Abusaleh M. Jabir, Jimson Mathew

J. Low Power Electron., 2017

Parasitic effects on memristive logic architecture.

Xiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Reliable gas sensing with memristive array.

Adedotun Adeyemo, Abusaleh M. Jabir, Jimson Mathew, Eugenio Martinelli, Corrado Di Natale, Marco Ottavi

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Learning method for ex-situ training of memristor crossbar based multi-layer neural network.

Anu Bala, Adedotun Adeyemo, Xiaohan Yang, Abusaleh M. Jabir

Proceedings of the 9th International Congress on Ultra Modern Telecommunications and Control Systems and Workshops, 2017

2016

Novel memristive logic architectures.

Xiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

High level abstraction of memristor model for neural network simulation.

Anu Bala, Adedotun Adeyemo, Xiaohan Yang, Abusaleh M. Jabir

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Analytic models for crossbar write operation.

Adedotun Adeyemo, Xiaohan Yang, Anu Bala, Abusaleh M. Jabir

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Analytic models for crossbar read operation.

Adedotun Adeyemo, Xiaohan Yang, Anu Bala, Jimson Mathew, Abusaleh M. Jabir

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

2015

A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2^m).

Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan

IEEE Trans. Very Large Scale Integr. Syst., 2015

Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays.

Adedotun A. Adeyemo, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014

Write scheme for multiple Complementary Resistive Switch (CRS) cells.

Adedotun Adeyemo, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan

Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

2013

Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity.

Jimson Mathew, Saraju P. Mohanty, Shibaji Banerjee, Dhiraj K. Pradhan, Abusaleh M. Jabir

Comput. Electr. Eng., 2013

2012

VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases.

Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies.

Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Saraju P. Mohanty

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Low complexity cross parity codes for multiple and random bit error correction.

Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Saraju P. Mohanty

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011

BCH code based multiple bit error correction in finite field multiplier circuits.

Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan, Saraju P. Mohanty

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields.

Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

Simplified bit parallel systolic multipliers for special class of galois field (2^m) with testability.

Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan

IET Comput. Digit. Tech., 2010

A Galois field-based logic synthesis with testability.

Jimson Mathew, Abusaleh M. Jabir, Ashutosh Kumar Singh, Hafizur Rahaman, Dhiraj K. Pradhan

IET Comput. Digit. Tech., 2010

On the synthesis of attack tolerant cryptographic hardware.

Jimson Mathew, Savita Banerjee, Hafizur Rahaman, Dhiraj K. Pradhan, Saraju P. Mohanty, Abusaleh M. Jabir

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

On the design of different concurrent EDC schemes for S-Box and GF(p).

Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir, Saraju P. Mohanty, Dhiraj K. Pradhan

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009

Single error correctable bit parallel multipliers over GF(2^m).

Jimson Mathew, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan

IET Comput. Digit. Tech., 2009

C-testable S-box implementation for secure advanced encryption standard.

Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008

C-testable bit parallel multipliers over <i>GF</i>(2^<i>m</i>).

Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir

ACM Trans. Design Autom. Electr. Syst., 2008

GfXpress: A Technique for Synthesis and Optimization of GF(2^m) Polynomials.

Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m).

Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir

IEEE Trans. Computers, 2008

A Galois Field Based Logic Synthesis Approach with Testability.

Jimson Mathew, Hafizur Rahaman, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Single Error Correcting Finite Field Multipliers Over GF(2m).

Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Fault tolerant bit parallel finite field multipliers using LDPC codes.

Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection.

Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

2007

A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation.

Abusaleh M. Jabir, Dhiraj K. Pradhan, T. L. Rajaprabhu, Ashutosh Kumar Singh

IEEE Trans. Computers, 2007

A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields.

Abusaleh M. Jabir, Dhiraj K. Pradhan

IEEE Trans. Computers, 2007

2006

An efficient technique for synthesis and optimization of polynomials in GF(2^<i>m</i>).

Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Easily Testable Implementation for Bit Parallel Multipliers in GF (2m).

Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2005

GASIM: a fast Galois field based simulator for functional model.

Dhiraj K. Pradhan, Ashutosh Kumar Singh, T. L. Rajaprabhu, Abusaleh M. Jabir

Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

2004

MODD for CF: a representation for fast evaluation of multiple-output functions.

T. L. Rajaprabhu, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions.

Abusaleh M. Jabir, Dhiraj K. Pradhan

Proceedings of the 2004 Design, 2004

2001

Logic minimization algorithms for three-level AND-OR-EXOR representations.

Abusaleh M. Jabir

PhD thesis, 2001