Seema Butala Anand

According to our database1, Seema Butala Anand authored at least 8 papers between 2000 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2010

2008
A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 µm CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit.
IEEE J. Solid State Circuits, 2008

2007

2006
On the Dynamics of Regenerative Frequency Dividers.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

2005
A fully integrated SOC for 802.11b in 0.18-μm CMOS.
IEEE J. Solid State Circuits, 2005

2003
A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard.
IEEE J. Solid State Circuits, 2003

2001
A CMOS clock recovery circuit for 2.5-Gb/s NRZ data.
IEEE J. Solid State Circuits, 2001

2000
A 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-μm CMOS technology.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000


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