Mark Chambers

According to our database, Mark Chambers authored at least 6 papers between 1996 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2017

A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.

Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori

IEEE J. Solid State Circuits, 2017

2016

19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.

Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS.

Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori

IEEE J. Solid State Circuits, 2015

2014

A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS.

Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori

Proceedings of the Symposium on VLSI Circuits, 2014

2008

A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 µm CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit.

Ali Afsahi, Jacob J. Rael, Arya Behzad, Hung-Ming Chien, Michael Pan, Stephen Au, Adedayo Ojo, C. Paul Lee, Seema Butala Anand, Kevin Chien, Stephen Wu, Rozi Roufoogaran, Alireza Zolfaghari, John C. Leete, Long H. Tran, Keith A. Carter, Mohammad Nariman, David W. K. Yeung, Walter Morton, Mark Gonikberg, Mukul Seth, Marcellus Forbes, Jay Pattin, Luis Gutierrez, Sumant Ranganathan, Ning Li, Eric Blecker, Jack Lin, Tom Kwan, Rose Zhu, Mark Chambers, Maryam Rofougaran, Ahmadreza Rofougaran, Jason Trachewsky, Pieter van Rooyen

IEEE J. Solid State Circuits, 2008

1996

A PRML read/write channel IC using analog signal processing for 200 Mb/s HDD.

Kavch Parsi, Robert P. Burns, Alan Chaiken, Mark Chambers, William R. Forni, David Harnishfeger, Scott Kaylor, Micheal J. Pennell, Jose O. Perez, Narendra Rao, Mark Rohrhaugh, Mike Ross, Gary L. Stuhlmiller

IEEE J. Solid State Circuits, 1996