Seiji Miura

According to our database, Seiji Miura authored at least 7 papers between 2001 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

A 7nm CMOS Anomaly-Detection Deep-Learning Processor with Embedded A/D Converters and Pseudo-Image Generation for Sensor Fusion.

Takashi Oshima, Keisuke Yamamoto, Seiji Miura, Keita Yamane, Goichi Ono

Proceedings of the 51st Annual Conference of the IEEE Industrial Electronics Society, 2025

2021

Edge devices object detection by filter pruning.

Viviana Crescitelli, Seiji Miura, Goichi Ono, Naohiro Kohmu

Proceedings of the 26th IEEE International Conference on Emerging Technologies and Factory Automation, 2021

2018

Efficient Data-Allocation Scheme for Eliminating Garbage Collection During Analysis of Big Graphs Stored in NAND Flash Memory.

Hiroshi Uchigaito, Seiji Miura, Takumi Nito

IEEE Trans. Computers, 2018

2015

A control scheme for eliminating garbage collection during highspeed analysis of big-graph data stored in NAND flash memory.

Hiroshi Uchigaito, Seiji Miura, Takumi Nito

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2005

A memory controller that reduces latency of cached SDRAM.

Seiji Miura, Satoru Akiyama

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Elastic shared resource scheduling SOC interconnect architecture for real-time system.

Makoto Saen, Hiroshi Ueda, Masaru Hase, Eiji Yamamoto, Yoshihiro Mori, Hiroshi Hatae, Yuki Kondo, Seiji Miura, Itaru Nonomura, Naohiko Irie, Hiromi Watanabe

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2001

A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU.

Seiji Miura, Kazushige Ayukawa, Takao Watanabe

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001