Satoru Akiyama

According to our database, Satoru Akiyama authored at least 7 papers between 2005 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2012

A Low-<i>V</i>_t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing.

Satoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh

IEICE Trans. Electron., 2012

2010

0.5-V Low- V _T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays.

Akira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi

IEEE J. Solid State Circuits, 2010

2009

Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays.

Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007

Long-Retention-Time, High-Speed DRAM Array with 12-<i>F</i>² Twin Cell for Sub 1-V Operation.

Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara

IEICE Trans. Electron., 2007

2006

Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM.

Satoru Akiyama, Tomonori Sekiguchi, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara

IEEE J. Solid State Circuits, 2006

2005

The Umbrella Cell: A High-Density 2T Cell for SOC Applications.

Satoru Akiyama, Takao Watanabe, Nobuhiro Oodaira, Tsuyoshi Ishikawa, Digh Hisamoto

IEICE Trans. Electron., 2005

A memory controller that reduces latency of cached SDRAM.

Seiji Miura, Satoru Akiyama

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005