Goichi Ono

According to our database1, Goichi Ono authored at least 26 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A 0.75V 0.016mm<sup>2</sup> 12ENOB 7nm CMOS cyclic ADC with 1.5bit passive amplification stage and dynamic capacitance scaling.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2021
Edge devices object detection by filter pruning.
Proceedings of the 26th IEEE International Conference on Emerging Technologies and Factory Automation, 2021

2014
A Method for Measuring of RTN by Boosting Word-Line Voltage in 6-Tr-SRAMs.
IEICE Trans. Electron., 2014

2011
A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link.
IEEE J. Solid State Circuits, 2011

Accurate TOA Estimating UWB-IR Transceiver for Ranging System in Multi-Path Environment.
IEICE Trans. Commun., 2011

10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process.
IEEE J. Solid State Circuits, 2010

100GbE PHY and MAC layer implementations.
IEEE Commun. Mag., 2010

A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 25 Gbps inductorless receiver front-end in 65-nm CMOS for serial links.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Intermittent Operation Control Scheme for Reducing Power Consumption of UWB-IR Receiver.
IEEE J. Solid State Circuits, 2009

A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS.
IEEE J. Solid State Circuits, 2009

1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver.
IEICE Trans. Electron., 2009

10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1<sup>st</sup>-order ΔΣ modulator.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

UWB-IR Receiver with Accurate Time-interval-measurement Circuit for Communication/location System.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
1-cc Computer: Cross-Layer Integration With UWB-IR Communication and Locationing.
IEEE J. Solid State Circuits, 2008

0.7-GHz-Bandwidth DS-UWB-IR System for Low-Power Wireless Communications.
IEICE Trans. Commun., 2008

1-cc computer using UWB-IR for wireless sensor network.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
1-GHz Input bandwidth 6-bit under-sampling A/D converter for UWB-IR receiver.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2005
An LSI system with locked in temperature insensitive state achieved by using body bias technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Optimum threshold-voltage tuning for low-power, high-performance microprocessor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Electric power generation using piezoelectric resonator for power-free sensor node.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Temperature referenced supply voltage and forward-body-bias control (TSFC) architecture for minimum power consumption [ubiquitous computing processors].
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2003
Threshold-voltage balance for minimum supply operation [LV CMOS chips].
IEEE J. Solid State Circuits, 2003

Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experiment.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2002
A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias.
IEEE J. Solid State Circuits, 2002


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