Sergio Nocco

ACM Trans. Design Autom. Electr. Syst., 2013

2011

Benchmarking a model checker for algorithmic improvements and tuning for performance.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2011

Interpolation sequences revisited.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Optimized model checking of multiple properties.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

A Novel SAT-Based Approach to the Task Graph Cost-Optimal Scheduling Problem.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Partitioning Interpolant-Based Verification for Effective Unbounded Model Checking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Finding Multiple Equivalence-Preserving Transformations in Combinational Circuits through Incremental-SAT.

[BibT_eX]

[DOI]

J. Electron. Test., 2010

2009

Strengthening Model Checking Techniques With Inductive Invariants.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Exploiting incrementality in SAT-based search for multiple equivalence-preserving transformations in combinational circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

Speeding up model checking by exploiting explicit and hidden verification constraints.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Boosting interpolation with dynamic localized abstraction and redundancy removal.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

A Probabilistic and Approximated Approach to Circuit-Based Formal Verification.

[BibT_eX]

[DOI]

J. Satisf. Boolean Model. Comput., 2008

Stressing Symbolic Scheduling Techniques within Aircraft Maintenance Optimization.

[BibT_eX]

[DOI]

J. Satisf. Boolean Model. Comput., 2008

Trading-Off SAT Search and Variable Quantifications for Effective Unbounded Model Checking.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2008

2007

Boosting the role of inductive invariants in model checking.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Stepping forward with interpolants in unbounded model checking.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005

Symbolic reachability analysis techniques within the fields of formal verification and automated scheduling.

[BibT_eX]

[DOI]

PhD thesis, 2005

Are BDDs still alive within sequential verification?

[BibT_eX]

[DOI]

Int. J. Softw. Tools Technol. Transf., 2005

A BMC-based formulation for the scheduling problem of hardware systems.

[BibT_eX]

[DOI]

Int. J. Softw. Tools Technol. Transf., 2005

Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

2004

Exploiting Target Enlargement and Dynamic Abstraction within Mixed BDD and SAT Invariant Checking.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Workshop on Bounded Model Checking, 2004

2003

A BMC-formulation for the scheduling problem in highly constrained hardware Systems.

[BibT_eX]

[DOI]

Proceedings of the First International Workshop on Bounded Model Checking, 2003

Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

2002

A Symbolic Approach for the Combined Solution of Scheduling and Allocation.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Mixing Forward and Backward Traversals in Guided-Prioritized BDD-Based Verification.

[BibT_eX]

[DOI]