Mihai T. Lazarescu

Orcid: 0000-0003-0884-5158

According to our database1, Mihai T. Lazarescu authored at least 46 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2023
Design and Optimization of Residual Neural Network Accelerators for Low-Power FPGAs Using High-Level Synthesis.
CoRR, 2023

Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops.
IEEE Access, 2023

A Graph Neural Network Model for Fast and Accurate Quality of Result Estimation for High-Level Synthesis.
IEEE Access, 2023

Enhanced Exploration of Neural Network Models for Indoor Human Monitoring.
Proceedings of the 9th International Workshop on Advances in Sensors and Interfaces, 2023

A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

2022
Fast Energy-Optimal Multikernel DNN-Like Application Allocation on Multi-FPGA Platforms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio.
IEEE Access, 2022

Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs.
IEEE Access, 2022

2021
CNN-on-AWS: Efficient Allocation of Multikernel Applications on Multi-FPGA Platforms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Asynchronous Resilient Wireless Sensor Network for Train Integrity Monitoring.
IEEE Internet Things J., 2021

High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs.
IEEE Access, 2021

2020
Power-Optimal Mapping of CNN Applications to Cloud-Based Multi-FPGA Platforms.
IEEE Trans. Circuits Syst., 2020

Real-Time Sensor Networks and Systems for the Industrial IoT: What Next?
Sensors, 2020

Performance and energy-efficient implementation of a smart city application on FPGAs.
J. Real Time Image Process., 2020

Comparative node selection-based localization technique for wireless sensor networks: A bilateration approach.
Int. J. Commun. Syst., 2020

2019
Very Low Power Neural Network FPGA Accelerators for Tag-Less Remote Person Identification Using Capacitive Sensors.
IEEE Access, 2019

Neural network-based indoor tag-less localization using capacitive sensors.
Proceedings of the 2019 ACM International Joint Conference on Pervasive and Ubiquitous Computing and Proceedings of the 2019 ACM International Symposium on Wearable Computers, 2019

Exact and Heuristic Allocation of Multi-kernel Applications to Multi-FPGA Platforms.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Capacitive Sensor for Tagless Remote Human Identification Using Body Frequency Absorption Signatures.
IEEE Trans. Instrum. Meas., 2018

2017
Wireless Sensor Networks.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Performance of Machine Learning Classifiers for Indoor Person Localization With Capacitive Sensors.
IEEE Access, 2017

High-Level Synthesis for Semi-Global Matching: Is the Juice Worth the Squeeze?
IEEE Access, 2017

Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis.
IEEE Access, 2017

High sensitivity, low noise front-end for long range capacitive sensors for tagless indoor human localization.
Proceedings of the 3rd IEEE International Forum on Research and Technologies for Society and Industry, 2017

Long range, high sensitivity, low noise capacitive sensor for tagless indoor human localization.
Proceedings of the 7th IEEE International Workshop on Advances in Sensors and Interfaces, 2017

2016
Integrated Toolset for WSN Application Planning, Development, Commissioning and Maintenance: The WSN-DPCM ARTEMIS-JU Project.
Sensors, 2016

A Tagless Indoor Localization System Based on Capacitive Sensing Technology.
Sensors, 2016

2015
Virtual Platform-Based Design Space Exploration of Power-Efficient Distributed Embedded Applications.
ACM Trans. Embed. Comput. Syst., 2015

Interactive Trace-Based Analysis Toolset for Manual Parallelization of C Programs.
ACM Trans. Embed. Comput. Syst., 2015

Design and Field Test of a WSN Platform Prototype for Long-Term Environmental Monitoring.
Sensors, 2015

2014
Introduction to Special Issue on Application of Concurrency to System Design (ACSD'13).
ACM Trans. Embed. Comput. Syst., 2014

Improving the design flow for parallel and heterogeneous architectures running real-time applications: The PHARAON FP7 project.
Microprocess. Microsystems, 2014

Energy-aware parallelization flow and toolset for C code.
Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, 2014

2013
HEAP: A Highly Efficient Adaptive multi-Processor framework.
Microprocess. Microsystems, 2013

Design of a WSN Platform for Long-Term Environmental Monitoring for IoT Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013

EU FP7-288307 Pharaon Project: Parallel and Heterogeneous Architecture for Real-Time Applications.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Dynamic Trace-Based Data Dependency Analysis for Parallelization of C Programs.
Proceedings of the 12th IEEE International Working Conference on Source Code Analysis and Manipulation, 2012

FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

SystemC Model Generation for Realistic Simulation of Networked Embedded Systems.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Network-aware design-space exploration of a power-efficient embedded application.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2010
Energy optimization at the MAC layer for a forest fire monitoring wireless sensor network.
Proceedings of 15th IEEE International Conference on Emerging Technologies and Factory Automation, 2010

2002
A Symbolic Approach for the Combined Solution of Scheduling and Allocation.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

2000
Compilation-based software performance estimation for system level design.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

Software performance estimation strategies in a system-level design tool.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999
A compilation-based software estimation scheme for hardware/software co-simulation.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
Electric power quality assessment and data transmission over low voltage mains.
PhD thesis, 1998


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