Shah M. Jahinuzzaman

According to our database1, Shah M. Jahinuzzaman authored at least 11 papers between 2006 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2015
Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2012
A read-decoupled gated-ground SRAM architecture for low-power embedded memories.
Integr., 2012

2011
A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A 7T SRAM bit-cell for low-power embedded memories.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010
A scalable offset-cancelled current/voltage sense amplifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC.
IEEE J. Solid State Circuits, 2009

2008
Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A multiword based high speed ECC scheme for low-voltage embedded SRAMS.
Proceedings of the ESSCIRC 2008, 2008

2007
Dynamic Data Stability in Low-power SRAM Design.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006


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