Jaspal Singh Shah

According to our database1, Jaspal Singh Shah authored at least 5 papers between 2008 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
Radiation hardened pulsed-latches in 65-nm CMOS.
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

2013
An Energy-Efficient Offset-Cancelling Sense Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

2012
A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

2009
Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC.
IEEE J. Solid State Circuits, 2009

2008
A multiword based high speed ECC scheme for low-voltage embedded SRAMS.
Proceedings of the ESSCIRC 2008, 2008


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