David Rennie

According to our database1, David Rennie authored at least 9 papers between 2007 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2012
Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2011
Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2009
Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC.
IEEE J. Solid State Circuits, 2009

2008
A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

2007
Analysis and Design of Robust Multi-Gb/s Clock and Data Recovery Circuits.
PhD thesis, 2007

Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Low Voltage Buffered Bandgap Reference.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A Novel Tri-State Binary Phase Detector.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007


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