According to our database1, Shahaboddin Moazzeni authored at least 7 papers between 2012 and 2020.
Legend:Book In proceedings Article PhD thesis Other
A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2020
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
A 28µW sub-sampling based wake-up receiver with -70dBm sensitivity for 915MHz ISM band applications.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012