Chih-Chang Lin

According to our database1, Chih-Chang Lin authored at least 17 papers between 1994 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Design Guidelines of Social-Assisted Robots for the Elderly: A Mixed Method Systematic Literature Review.
Proceedings of the HCI International 2020 - Late Breaking Papers: Cognition, Learning and Games, 2020

2019
A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2014
8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012
A 2.7GHz 3.9mW Mesh-BJT LC-VCO with -204dBc/Hz FOM in 65nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

1999
Logic synthesis for engineering change.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998
Cost-free scan: a low-overhead scan path design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Test-point insertion: scan paths through functional logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs.
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

1997
On designing universal logic blocks and their application to FPGA design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1996
Sequential Permissible Functions and their Application to Circuit Optimization.
Proceedings of the 1996 European Design and Test Conference, 1996

Test Point Insertion: Scan Paths through Combinational Logic.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Cost-free scan: a low-overhead scan path design methodology.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Circuit partitioning with logic perturbation.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Logic Synthesis for Engineering Change.
Proceedings of the 32st Conference on Design Automation, 1995

Logic rectification and synthesis for engineering change.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Universal logic gate for FPGA design.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994


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