Ming-Chieh Huang

According to our database1, Ming-Chieh Huang authored at least 5 papers between 2003 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2014
8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012
A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

A 2.7GHz 3.9mW Mesh-BJT LC-VCO with -204dBc/Hz FOM in 65nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2003
Estimate of process compositions and plantwide control from multiple secondary measurements using artificial neural networks.
Comput. Chem. Eng., 2003


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