Shalina Percy Delicia

Orcid: 0000-0002-2626-603X

According to our database1, Shalina Percy Delicia authored at least 8 papers between 2015 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
An Efficient High-Throughput Generic QAM Transmitter with Scalable Spiral FIR Filter.
J. Circuits Syst. Comput., 2019

2018
Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
A reconfigurable high-speed spiral FIR filter architecture.
Proceedings of the 40th International Conference on Telecommunications and Signal Processing, 2017

Parameter Sensitivity in Virtual FPGA Architectures.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
A variable FPGA based generic QAM transmitter with scalable mixed time and frequency domain signal processing.
Proceedings of the 39th International Conference on Telecommunications and Signal Processing, 2016

2015
A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Parametric design space exploration for optimizing QAM based high-speed communication.
Proceedings of the 2015 IEEE/CIC International Conference on Communications in China, 2015

TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015


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