Lisa Wu Wills

Affiliations:
  • Duke University, NC, USA
  • Columbia University, NY, USA (former)
  • UC Berkeley, CA, USA (former)
  • University of Michigan, Ann Arbor, MI, USA (former)


According to our database1, Lisa Wu Wills authored at least 13 papers between 2001 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2021
Accelerating Genomic Data Analytics With Composable Hardware Acceleration Framework.
IEEE Micro, 2021

2020
Guest Editorial: IEEE TC Special Issue on Domain-Specific Architectures for Emerging Applications.
IEEE Trans. Computers, 2020

Genesis: A Hardware Acceleration Framework for Genomic Data Analysis.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2019
FPGA Accelerated INDEL Realignment in the Cloud.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2016
Graphicionado: A high-performance and energy-efficient accelerator for graph analytics.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

2015
The Q100 Database Processing Unit.
IEEE Micro, 2015

2014
Energy Analysis of Hardware and Software Range Partitioning.
ACM Trans. Comput. Syst., 2014

Hardware Partitioning for Big Data Analytics.
IEEE Micro, 2014

Q100: the architecture and design of a database processing unit.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2013
Navigating big data with high-throughput, energy-efficient data partitioning.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012
Cache Impacts of Datatype Acceleration.
IEEE Comput. Archit. Lett., 2012

2001
CryptoManiac: a fast flexible architecture for secure communication.
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

Application specific architectures: a recipe for fast, flexible and power efficient designs.
Proceedings of the 2001 International Conference on Compilers, 2001


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