Shien Zhu

According to our database, Shien Zhu authored at least 16 papers between 2020 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

FPGA-Accelerated Lock Management and Transaction Processing: Architecture, Optimization, and Design Space Exploration.

Shien Zhu, Gustavo Alonso

CoRR, May, 2026

TABv2: A Faster Ternary and Binary Neural Network Inference Library on the Edge.

Guanshujie Fu, Olivier Fischer, Shien Zhu, Gustavo Alonso

IEEE Trans. Very Large Scale Integr. Syst., April, 2026

SSR: Sparse Segment Reduction for Ternary GEMM Acceleration.

Adeline Pittet, Shien Zhu, Valérie Verdan, Gustavo Alonso

Proceedings of the Design, Automation & Test in Europe Conference, 2026

2025

Exploring Large Language Models for Hierarchical Hardware Circuit and Testbench Generation.

Samuel Gomes Lopes, Shien Zhu, Gustavo Alonso

ACM Trans. Design Autom. Electr. Syst., November, 2025

Pre-Attention Expert Prediction and Prefetching for Mixture-of-Experts Large Language Models.

Shien Zhu, Samuel Bohl, Robin Oester, Gustavo Alonso

CoRR, November, 2025

Faster Ternary and Binary Neural Network Inference on CPU by Reducing Popcount Overhead.

Olivier Fischer, Shien Zhu, Gustavo Alonso

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2025

2023

FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks.

Shien Zhu, Luan H. K. Duong, Hui Chen, Di Liu, Weichen Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023

iMAT: Energy-Efficient In-Memory Acceleration for Ternary Neural Networks With Sparse Dot Product.

Shien Zhu, Shuo Huai, Guochu Xiong, Weichen Liu

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

An Efficient Sparse LSTM Accelerator on Embedded FPGAs with Bandwidth-Oriented Pruning.

Shiqing Li, Shien Zhu, Xiangzhong Luo, Tao Luo, Weichen Liu

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

2022

TAB: Unified and Optimized Ternary, Binary, and Mixed-precision Neural Network Inference on the Edge.

Shien Zhu, Luan H. K. Duong, Weichen Liu

ACM Trans. Embed. Comput. Syst., September, 2022

Deep learning acceleration: from quantization to in-memory computing

Shien Zhu

PhD thesis, 2022

EDLAB: A Benchmark for Edge Deep Learning Accelerators.

Hao Kong, Shuo Huai, Di Liu, Lei Zhang, Hui Chen, Shien Zhu, Shiqing Li, Weichen Liu, Manu Rastogi, Ravi Subramaniam, Madhu Athreya, M. Anthony Lewis

IEEE Des. Test, 2022

iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations.

Shien Zhu, Shiqing Li, Weichen Liu

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021

Parallel Multipath Transmission for Burst Traffic Optimization in Point-to-Point NoCs.

Hui Chen, Zihao Zhang, Peng Chen, Shien Zhu, Weichen Liu

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020

Cross-filter compression for CNN inference acceleration.

Fuyuan Lyu, Shien Zhu, Weichen Liu

CoRR, 2020

XOR-Net: An Efficient Computation Pipeline for Binary Neural Network Inference on Edge Devices.

Shien Zhu, Luan H. K. Duong, Weichen Liu

Proceedings of the 26th IEEE International Conference on Parallel and Distributed Systems, 2020