Shien Zhu

Orcid: 0000-0002-2094-7643

According to our database1, Shien Zhu authored at least 10 papers between 2020 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023

iMAT: Energy-Efficient In-Memory Acceleration for Ternary Neural Networks With Sparse Dot Product.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

An Efficient Sparse LSTM Accelerator on Embedded FPGAs with Bandwidth-Oriented Pruning.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

2022
TAB: Unified and Optimized Ternary, Binary, and Mixed-precision Neural Network Inference on the Edge.
ACM Trans. Embed. Comput. Syst., September, 2022

Deep learning acceleration: from quantization to in-memory computing
PhD thesis, 2022

EDLAB: A Benchmark for Edge Deep Learning Accelerators.
IEEE Des. Test, 2022

iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
Parallel Multipath Transmission for Burst Traffic Optimization in Point-to-Point NoCs.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
Cross-filter compression for CNN inference acceleration.
CoRR, 2020

XOR-Net: An Efficient Computation Pipeline for Binary Neural Network Inference on Edge Devices.
Proceedings of the 26th IEEE International Conference on Parallel and Distributed Systems, 2020


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