Shiqing Li

Orcid: 0000-0002-2081-8737

According to our database1, Shiqing Li authored at least 20 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Efficient FPGA-Based Sparse Matrix-Vector Multiplication With Data Reuse-Aware Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

An Efficient Gustavson-Based Sparse Matrix-Matrix Multiplication Accelerator on Embedded FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

CRIMP: Compact & Reliable DNN Inference on In-Memory Processing via Crossbar-Aligned Compression and Non-ideality Adaptation.
ACM Trans. Embed. Comput. Syst., October, 2023

A Comprehensive Memory Management Framework for CPU-FPGA Heterogenous SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

Model-Based Condition Monitoring of the Sensors and Actuators of an Electric and Automated Vehicle.
Sensors, January, 2023

An Efficient Sparse LSTM Accelerator on Embedded FPGAs with Bandwidth-Oriented Pruning.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Accelerating Gustavson-based SpMM on Embedded FPGAs with Element-wise Parallelism and Access Pattern-aware Caches.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

MUGNoC: A Software-Configured Multicast-Unicast-Gather NoC for Accelerating CNN Dataflows.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
EDLAB: A Benchmark for Edge Deep Learning Accelerators.
IEEE Des. Test, 2022

iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
MARCO: A High-performance Task Mapping and Routing Co-optimization Framework for Point-to-Point NoC-based Heterogeneous Computing Systems.
ACM Trans. Embed. Comput. Syst., 2021

Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Automated detection and analysis of social behaviors among preweaning piglets using key point-based spatial and temporal features.
Comput. Electron. Agric., 2021

Partial order based non-preemptive communication scheduling towards real-time networks-on-chip.
Proceedings of the SAC '21: The 36th ACM/SIGAPP Symposium on Applied Computing, 2021

Optimized Data Reuse via Reordering for Sparse Matrix-Vector Multiplication on FPGAs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020
Meta-Learning for Natural Language Understanding under Continual Learning Framework.
CoRR, 2020

2019
A New Intelligent Trajectory Planning Algorithm Based on Bug2 Algorithm: Bridge Algorithm.
Proceedings of the 2019 IEEE International Conference on Robotics and Biomimetics, 2019

Automatic data placement for CPU-FPGA heterogeneous multiprocessor System-on-Chips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
NVM-Based FPGA Block RAM With Adaptive SLC-MLC Conversion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2014
A 3D audio coding technique based on extracting the distance parameter.
Proceedings of the IEEE International Conference on Multimedia and Expo, 2014


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