Shijie Zhou

Affiliations:
  • Microsoft Corporation, Redmond, USA
  • University of Southern California, Los Angeles, CA, USA (PhD 2018)


According to our database1, Shijie Zhou authored at least 27 papers between 2013 and 2020.

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Bibliography

2020
Accelerating Stochastic Gradient Descent Based Matrix Factorization on FPGA.
IEEE Trans. Parallel Distributed Syst., 2020

2019
HitGraph: High-throughput Graph Processing Framework on FPGA.
IEEE Trans. Parallel Distributed Syst., 2019

2018
FASTCF: FPGA-based Accelerator for STochastic-Gradient-Descent-based Collaborative Filtering.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

An FPGA framework for edge-centric graph processing.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017
Accelerating Graph Analytics on CPU-FPGA Heterogeneous Platform.
Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017

Accelerating low rank matrix completion on FPGA.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Design and implementation of parallel PageRank on multicore platforms.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

Quickly finding a truss in a haystack.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

2016
High-Throughput and Energy-Efficient Graph Processing on FPGA.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015
Packet Classification on Multi-core Platforms.
Proceedings of the Handbook on Data Centers, 2015

A Decomposition-Based Approach for Scalable Many-Field Packet Classification on Multi-core Processors.
Int. J. Parallel Program., 2015

Optimizing memory performance for FPGA implementation of pagerank.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Accelerating Large-Scale Single-Source Shortest Path on FPGA.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

High-Throughput Online Hash Table on FPGA.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Scalable GPU-Accelerated IPv6 Lookup Using Hierarchical Perfect Hashing.
Proceedings of the 2015 IEEE Global Communications Conference, 2015

Large-scale packet classification on FPGA.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

Optimizing Many-field Packet Classification on FPGA, Multi-core General Purpose Processor, and GPU.
Proceedings of the Eleventh ACM/IEEE Symposium on Architectures for networking and communications systems, 2015

2014
Multi-core implementation of decomposition-based packet classification algorithms.
J. Supercomput., 2014

A programmable and scalable openflow switch using heterogeneous soc platforms.
Proceedings of the third workshop on Hot topics in software defined networking, 2014

High-Performance Traffic Classification on GPU.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

400 Gbps energy-efficient multi-field packet classification on FPGA.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

A flexible and scalable high-performance OpenFlow switch on heterogeneous SoC platforms.
Proceedings of the IEEE 33rd International Performance Computing and Communications Conference, 2014

Performance modeling and optimizations for decomposition-based large-scale packet classification on multi-core processors.
Proceedings of the IEEE 15th International Conference on High Performance Switching and Routing, 2014

High-performance packet classification on GPU.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

Energy performance of FPGAs on PERFECT suite kernels.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

2013
Scalable Many-Field Packet Classification on Multi-core Processors.
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

High-performance architecture for dynamically updatable packet classification on FPGA.
Proceedings of the Symposium on Architecture for Networking and Communications Systems, 2013


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