Shin-Hyun Jeong

Orcid: 0000-0003-2998-8342

According to our database1, Shin-Hyun Jeong authored at least 6 papers between 2019 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021
A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface.
IEEE J. Solid State Circuits, 2021

A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface.
IEEE Access, 2021

A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

2019
A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019


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