Sungphil Choi
Orcid: 0000-0001-7857-8783
According to our database1,
Sungphil Choi
authored at least 7 papers
between 2018 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
2022
A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
2021
A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface.
IEEE Access, 2021
2020
A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
2019
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
2018
A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller.
IEEE Trans. Circuits Syst. II Express Briefs, 2018