Yong-Un Jeong
Orcid: 0000-0003-0472-0542Affiliations:
- Seoul National University, South Korea
According to our database1,
Yong-Un Jeong
authored at least 16 papers
between 2017 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces.
IEEE J. Solid State Circuits, September, 2023
2022
A Low-Power DRAM Transmitter With Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces.
IEEE Access, 2022
Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters.
IEEE Access, 2022
2021
A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface.
IEEE J. Solid State Circuits, 2021
A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface.
IEEE Access, 2021
A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Data-Dependent Selection of Amplitude and Phase Equalization in a Quarter-Rate Transmitter for Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
A 28-Gb/s/pin PAM-4 Single-Ended Transmitter with High-Linearity and Impedance-Matched Driver and 3-Point ZQ Calibration for Memory Interfaces.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
2018
A 2.1-Gb/s 12-Channel Transmitter With Phase Emphasis Embedded Serializer for 55-in UHD Intra-Panel Interface.
IEEE J. Solid State Circuits, 2018
2017
A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017