Shixiong Jiang

Orcid: 0009-0004-9137-2359

According to our database1, Shixiong Jiang authored at least 21 papers between 2012 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Vulnerability Analysis of Safe Reinforcement Learning via Inverse Constrained Reinforcement Learning.
CoRR, February, 2026

A Joint Scheduling Framework for Electric Bus Fleets and Charging Infrastructure in Urban Transit Systems.
Syst., 2026

2025
Query-Based Black-Box Stealthy Sensor Attacks on Cyber-Physical Systems.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024
Backdoor Attacks on Safe Reinforcement Learning-Enabled Cyber-Physical Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024

CPSim: Simulation Toolbox for Security Problems in Cyber-Physical Systems.
ACM Trans. Design Autom. Electr. Syst., 2024

Demo: Vulnerability Analysis for STL-Guided Safe Reinforcement Learning in Cyber-Physical Systems.
Proceedings of the 30th IEEE Real-Time and Embedded Technology and Applications Symposium, 2024

Vulnerability Analysis for Safe Reinforcement Learning in Cyber-Physical Systems.
Proceedings of the 15th ACM/IEEE International Conference on Cyber-Physical Systems, 2024

2020
Modeling Concurrent Day-to-Day Departure Time and Route Choices With Multiple Micro-Preferences.
IEEE Access, 2020

Forecasting the Short-Term Metro Ridership With Seasonal and Trend Decomposition Using Loess and LSTM Neural Networks.
IEEE Access, 2020

2019
Energy-efficient and reliable in-memory classifier for machine-learning applications.
IET Comput. Digit. Tech., 2019

An Energy Efficient In-Memory Computing Machine Learning Classifier Scheme.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2017
A multiagent-based model for pedestrian simulation in subway stations.
Simul. Model. Pract. Theory, 2017

2016
A fully parallel content addressable memory design using multi-bank structure.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

2015
TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Edge-aware dynamic programming-based cost aggregation for robust stereo matching.
J. Electronic Imaging, 2015

A novel fault-tolerant router architecture for network-on-chip reconfiguration.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A high throughput router with a novel switch allocator for network on chip.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A high speed and low power content-addressable memory(CAM) using pipelined scheme.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

2012
Ultra-Low Voltage Split-Data-Aware Embedded SRAM for Mobile Video Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Hybrid-cell register files design for improving NBTI reliability.
Microelectron. Reliab., 2012

Variation-and-aging aware low power embedded SRAM for multimedia applications.
Proceedings of the IEEE 25th International SOC Conference, 2012


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