Na Gong

According to our database1, Na Gong authored at least 45 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2020
Memory Optimization for Energy-Efficient Differentially Private Deep Learning.
IEEE Trans. Very Large Scale Integr. Syst., 2020

On Mathematical Models of Optimal Video Memory Design.
IEEE Trans. Circuits Syst. Video Technol., 2020

Run-Time Deep Learning Enhanced Fast Coding Unit Decision for High Efficiency Video Coding.
J. Circuits Syst. Comput., 2020

2019
Data-Pattern Enabled Self-Recovery Low-Power Storage System for Big Video Data.
IEEE Trans. Big Data, 2019

Mitigating Nonlinear Effect of Memristive Synaptic Device for Neuromorphic Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Content-Adaptive Memory for Viewer-Aware Energy-Quality Scalable Mobile Video Systems.
IEEE Access, 2019

Linear Optimization for Memristive Device in Neuromorphic Hardware.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Embedded sensory data memory optimization for IoT edge inference with privacy, accuracy, and energy efficiency.
Proceedings of the 4th ACM/IEEE Symposium on Edge Computing, 2019

2018
A Novel Hybrid Delay Unit Based on Dummy TSVs for 3-D On-Chip Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Viewer-Aware Intelligent Efficient Mobile Video Embedded Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Viewer-Aware Intelligent Mobile Video System for Prolonged Battery Life.
Proceedings of the Human Vision and Electronic Imaging 2018, Burlingame, CA, USA, 28 January 2018, 2018

2017
SPIDER: Sizing-Priority-Based Application-Driven Memory for Mobile Video Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Data-Driven Intelligent Efficient Synaptic Storage for Deep Learning.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Design and performance analysis of energy harvesting sensor networks with supercapacitor.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

On-chip thermal management method based on phase change material.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Closed form delay models for buffer-driven TSVs in 3D on-chip memory.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016
PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low-Power Microprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2016

cNV SRAM: CMOS Technology Compatible Non-Volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory System.
IEEE Trans. Computers, 2016

Sizing-priority based low-power embedded memory for mobile video applications.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Data-Driven Low-Cost On-Chip Memory with Adaptive Power-Quality Trade-off for Mobile Video Streaming.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Luminance-adaptive smart video storage system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Data-Pattern enabled Self-Recovery multimedia storage system for near-threshold computing.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

RF-powered battery-less Wireless Sensor Network in structural monitoring.
Proceedings of the 2016 IEEE International Conference on Electro Information Technology, 2016

Dummy TSV based bit-line optimization in 3D on-chip memory.
Proceedings of the 2016 IEEE International Conference on Electro Information Technology, 2016

2015
TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2015

VCAS: Viewing context aware power-efficient mobile video embedded memory.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Reusable IO technique for improved utility of IC test circuit area.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Novel CMOS technology compatible nonvolatile on-chip hybrid memory.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

DCPG: Double-control power gating technique for a 28 nm Cortex™-A9 MPCore Quad-core processor.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A thermal-aware distribution method of TSV in 3D IC.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Variation Aware Sleep Vector Selection in Dual V<sub>t</sub> Dynamic OR Circuits for Low Leakage Register File Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013
Application-driven power efficient ALU design methodology for modern microprocessors.
Proceedings of the International Symposium on Quality Electronic Design, 2013

2012
Ultra-Low Voltage Split-Data-Aware Embedded SRAM for Mobile Video Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Hybrid-cell register files design for improving NBTI reliability.
Microelectron. Reliab., 2012

Variation-and-aging aware low power embedded SRAM for multimedia applications.
Proceedings of the IEEE 25th International SOC Conference, 2012

2011
Leakage current, active power, and delay analysis of dynamic dual V<sub>t</sub> CMOS circuits under P-V-T fluctuations.
Microelectron. Reliab., 2011

PVT variations aware optimal sleep vector determination of dual VT domino OR circuits.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Low power tri-state register files design for modern out-of-order processors.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Novel adaptive keeper LBL technique for low power and high performance register files.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

2010
Fan-in sensitive low power dynamic circuits performance statistical characterization.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Optimization and predication of leakage current characteristics in wide domino OR gates under PVT variation.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Domino gate with modified voltage keeper.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009
Estimation for Speed and Leakage Power of Dual Threshold Domino OR Based on Wavelet Neural Networks.
Proceedings of the Advances in Neural Networks, 2009

Switching and leakage power modeling for multiple-supply dynamic gate with delay constraining based on wavelet neural networks.
Proceedings of the International Joint Conference on Neural Networks, 2009

2008
Analysis and optimization of leakage current characteristics in sub-65 nm dual V<sub>t</sub> footed domino circuits.
Microelectron. J., 2008


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