According to our database1, Shizunori Matsumoto authored at least 4 papers between 2001 and 2018.
Legend:Book In proceedings Article PhD thesis Other
Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs.
4.9 A 1ms high-speed vision chip with 3D-stacked 140GOPS column-parallel PEs for spatio-temporal image processing.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
1/<i>f</i>-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation.
IEICE Trans. Electron., 2005
Correlation method of circuit-performance and technology fluctuations for improved design reliability.
Proceedings of ASP-DAC 2001, 2001