Shigetaka Kumashiro

Orcid: 0000-0003-1729-1361

According to our database1, Shigetaka Kumashiro authored at least 20 papers between 1993 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
Ultra Long-term Measurement Results of BTI-induced Aging Degradation on 7-nm Ring Oscillators.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2020
An Efficient and Accurate Time Step Control Method for Power Device Transient Simulation Utilizing Dominant Time Constant Approximation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2013
Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation.
IEICE Trans. Electron., 2013

A predictable compact model for non-monotonous Vth-Pelgrom plot of long channel halo-implanted transistors.
Proceedings of the International Symposium on Quality Electronic Design, 2013

2012
On-Chip In-Place Measurements of V<sub>th</sub> and Signal/Substrate Response of Differential Pair Transistors.
IEICE Trans. Electron., 2012

HiSIM-RP: A reverse-profiling based 1<sup>st</sup> principles compact MOSFET model and its application to variability analysis of 90nm and 40nm CMOS.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011
On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement.
IEICE Trans. Electron., 2011

A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits.
IEICE Trans. Electron., 2011

Accurate analysis of substrate sensitivity of active transistors in an analog circuit.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010
Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns.
IEICE Trans. Electron., 2010

2008
Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations.
Math. Comput. Simul., 2008

Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress.
IEICE Trans. Electron., 2008

2005
A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential.
IEICE Trans. Electron., 2005

1/<i>f</i>-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation.
IEICE Trans. Electron., 2005

MOSFET harmonic distortion analysis up to the non-quasi-static frequency regime.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003
Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Circuit Simulation Models for Coming MOSFET Generations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2001
Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

Correlation method of circuit-performance and technology fluctuations for improved design reliability.
Proceedings of ASP-DAC 2001, 2001

1993
Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993


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