Sadahiko Miura

According to our database, Sadahiko Miura authored at least 10 papers between 2007 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction.

Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEEE J. Solid State Circuits, 2015

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.

Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Hideo Sato, Shunsuke Fukami, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Proceedings of the Symposium on VLSI Circuits, 2015

2014

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications.

Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara, Keizo Kinoshita, Shunsuke Fukami, Sadahiko Miura, Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Tadahiko Sugibayashi

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing.

Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications.

Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE Electron. Express, 2013

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.

Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times.

Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

Proceedings of the Symposium on VLSI Circuits, 2012

A 3.14 um² 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture.

Shoun Matsunaga, Sadahiko Miura, Hiroaki Honjou, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Proceedings of the Symposium on VLSI Circuits, 2012

2009

A 90nm 12ns 32Mb 2T1MTJ MRAM.

Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Shinsaku Saito, Yuichi Ito, Sadahiko Miura, Yuko Kato, Kaoru Mori, Yasuaki Ozaki, Yosuke Kobayashi, Norikazu Ohshima, Keizo Kinoshita, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Katsumi Suemitsu, Shunsuke Fukami, Hiromitsu Hada, Tadahiko Sugibayashi, Naoki Kasai

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007

A 16-Mb Toggle MRAM With Burst Modes.

Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo, Tetsuhiro Suzuki, Katsumi Suemitsu, Tomonori Mukai, Kaoru Mori, Ryusuke Nebashi, Shunsuke Fukami, Norikazu Ohshima, Hiromitsu Hada, Nobuyuki Ishiwata, Naoki Kasai, Shuichi Tahara

IEEE J. Solid State Circuits, 2007