Shumpei Kawasaki

According to our database, Shumpei Kawasaki authored at least 5 papers between 1986 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications.

Kesami Hagiwara, Tomoichi Hayashi, Shumpei Kawasaki, Fumio Arakawa, Oleg Endo, Hayato Nomura, Akira Tsukamoto, Duong Nguyen, Binh Nguyen, Anh Tran, Hoan Hyunh, Ikuo Kudoh, Cong-Kha Pham

Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

1995

SH3: high code density, low power.

Atsushi Hasegawa, Ikuya Kawasaki, Kouji Yamada, Shinichi Yoshioka, Shumpei Kawasaki, Prasenjit Biswas

IEEE Micro, 1995

1989

A floating-point VLSI chip for the TRON architecture: an architecture for reliable numerical programming.

Shumpei Kawasaki, Mitsuru Watabe, Shigeki Morinaga

IEEE Micro, 1989

1986

Microprogrammable Processor for Object-Oriented Architecture.

Tohru Nojiri, Shumpei Kawasaki, Kousuke Sakoda

Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986

A User-Adaptable VLSI Engine for Artificial Intelligence.

Shumpei Kawasaki, Tohru Nojiri, Kousuke Sakoda

Proceedings of the Information Processing 86, 1986