Prasenjit Biswas

According to our database, Prasenjit Biswas authored at least 26 papers between 1983 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

A Mathematical Framework for Exploring Protein Folding Dynamics using Probabilistic Model Checking.

Prasenjit Biswas, Sarit Pal, Sunil P. Khatri

Proceedings of the 3rd International Conference on Information and Computer Technologies, 2020

2017

Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra.

Prasenjit Biswas, D. M. H. Walker

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

2016

JU_KS_Group@FIRE 2016: Consumer Health Information Search.

Kamal Sarkar, Debanjan Das, Indra Banerjee, Mamta Kumari, Prasenjit Biswas

Proceedings of the Working notes of FIRE 2016, 2016

2010

Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform.

Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan

Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform.

Prasenjit Biswas, Pramod P. Udupa, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2009

REDEFINE: Runtime reconfigurable polymorphic ASIC.

Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan

ACM Trans. Embed. Comput. Syst., 2009

Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT.

Alexander Fell, Prasenjit Biswas, Jugantor Chetia, S. K. Nandy, Ranjani Narayan

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.

Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan

Proceedings of the 2009 International Conference on Compilers, 2009

2000

SH-5: The 64-Bit SuperH Architecture.

Prasenjit Biswas, Atsushi Hasegawa, Srinivas Mandaville, Mark Debbage, Andy Sturges, Fumio Arakawa, Yasuhiko Saito, Kunio Uchiyama

IEEE Micro, 2000

1997

Functional verification of the superscalar SH-4 microprocessor.

Prasenjit Biswas, Andy Freeman, Kouji Yamada, Norio Nakagawa, Kunio Uchiyama

Proceedings of the Proceedings IEEE COMPCON 97, 1997

1995

SH3: high code density, low power.

Atsushi Hasegawa, Ikuya Kawasaki, Kouji Yamada, Shinichi Yoshioka, Shumpei Kawasaki, Prasenjit Biswas

IEEE Micro, 1995

1994

Cut and Side-Effects in a Data-Driven Implementation of Prolog.

Surapong Auwatanamongkol, Andrzej Ciepielewski, Prasenjit Biswas

New Gener. Comput., 1994

1993

An extended scheduling technique for software pipelining.

Dagung Lu, Prasenjit Biswas

Microprocess. Microprogramming, 1993

PARSA: A Parallel Program Scheduling and Assessment Environment.

Behrooz A. Shirazi, Krishna M. Kavi, Ali R. Hurson, Prasenjit Biswas

Proceedings of the 1993 International Conference on Parallel Processing, 1993

1992

A memory-mapped interprocessor communication architecture using FIFO RAMs.

Syhy-Chang Su, Prasenjit Biswas

Microprocess. Microprogramming, 1992

1991

A snooping cache coherency protocol for hierarchically organized multiprocessors.

Gautam Dewan, Prasenjit Biswas

Microprocessing and Microprogramming, 1991

A Hybrid Architecture and Adaptive Scheduling for Parallel Execution of Logic Programs.

Surapong Auwatanamongkol, Prasenjit Biswas

Proceedings of the International Conference on Parallel Processing, 1991

1990

Scheduling demand-driven parallel logic programs on transputers.

Shyh-Chang Su, Prasenjit Biswas

Microprocessing and Microprogramming, 1990

A demand-driven macro-dataflow schema for distributed graph reduction on multiple G-machines.

Prasenjit Biswas, Jin Chen

Microprocessing and Microprogramming, 1990

1989

Abstract machine LORAP II and experiments in process grain size determination for parallel execution of logic programs.

Chin-Feng Fan, Prasenjit Biswas

Proceedings of the IEEE International Workshop on Tools for Artificial Intelligence: Architectures, 1989

1988

A Fuzzy Hybrid Model for Pattern Classification.

Prasenjit Biswas, Arun K. Majumdar

Proceedings of the Pattern Recognition, 1988

A Data-Driven Parallel Execution Model for Logic Programs.

Chien-Chao Tseng, Prasenjit Biswas

Proceedings of the Logic Programming, 1988

A Scalable Abstract Machine Model to Support Limited-OR (LOR) / Restricted-AND Parallelism (RAP) in Logic Programs.

Prasenjit Biswas, Shyh-Chang Su, David Y. Y. Yun

Proceedings of the Logic Programming, 1988

LogDf: A Data-Driven Abstract Machine Model for Parallel Execution of Logic Programs.

Prasenjit Biswas, Chien-Chao Tseng

Proceedings of the International Conference on Fifth Generation Computer Systems, 1988

1985

Architectural support for variable addressing in Ada - A design approach.

Prasenjit Biswas, Subrata Dasgupta

Int. J. Parallel Program., 1985

1983

A supervised learning algorithm for hierarchical classification of fuzzy patterns.

Prasenjit Biswas, Arun K. Majumdar

Inf. Sci., 1983