Fumio Arakawa

According to our database1, Fumio Arakawa authored at least 22 papers between 1993 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications.
Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

2017
Foreword.
IEICE Transactions, 2017

2016
Parallel Design of Feedback Control Systems Utilizing Dead Time for Embedded Multicore Processors.
IEICE Transactions, 2016

Message from the program committee chairs.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

2014
Simple One-to-One Architecture for Parallel Execution of Embedded Control Systems.
Proceedings of the 2014 IEEE International Conference on Cyber-Physical Systems, 2014

Parallel design of control systems utilizing dead time for embedded multicore processors.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

Establishing a standard interface between multi-manycore and software tools - SHIM.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

Panel discussions: Toward wearable computing era, how COOL chip architecture and tools will evolve?
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

2011
Cool Chips.
IEEE Micro, 2011

2009
An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU.
Microprocessors and Microsystems - Embedded Hardware Design, 2009

2006
Development of processor cores for digital consumer appliances.
Systems and Computers in Japan, 2006

SH-X: An embedded processor core for consumer appliances.
J. Embedded Computing, 2006

Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core.
IEICE Transactions, 2006

2005
SH-X: an embedded processor core for consumer appliances.
SIGARCH Computer Architecture News, 2005

A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones.
IEICE Transactions, 2005

An Exact Leading Non-Zero Detector for a Floating-Point Unit.
IEICE Transactions, 2005

Low-Power Design of 90-nm SuperH Processor Core.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004
Transparent SOC: on-chip analyzing techniques and implementation for embedded processor.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

2000
SH-5: The 64-Bit SuperH Architecture.
IEEE Micro, 2000

1998
SH4 RISC multimedia microprocessor.
IEEE Micro, 1998

1993
The Gmicro/500 superscalar microprocessor with branch buffers.
IEEE Micro, 1993

Design Methodology for GMICROTM/500 TRON Microprocessor.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993


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