Shunli Ma

Orcid: 0000-0003-0751-2343

According to our database1, Shunli Ma authored at least 52 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
A 40nm 2TOPS/W Depth-Completion Neural Network Accelerator SoC With Efficient Depth Engine for Realtime LiDAR Systems.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2023

A 90- to 115-GHz superheterodyne receiver front-end for W-band imaging system in 28-nm complementary metal-oxide-semiconductor.
Int. J. Circuit Theory Appl., April, 2023

A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023

A 300MS/s 57.6dB SNDR Single-Channel SAR ADC with Accelerated SAR Logic.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

High Performance Bootstrap Switch for 14 bit SAR ADC with Redundancy in SMIC 180nm.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A 15GHz Class-C VCO with Two-stage Buffer in 0.15-μm GaAs.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Multi-channel 12-bits 100MS/s SAR ADC in 65nm CMOS.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

An Improved Delay Cell with Low Power Consumption and Strong Driving Capability.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A High Gain and Wide Bandwidth Dual-Power CMOS Op-amp for High-Speed ADCs Application.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
A 6.5-mm<sup>2</sup> 10.5-to-15.5-GHz Differential GaN PA With Coupled-Line-Based Matching Networks Achieving 10-W Peak P<sub>sat</sub> and 42% PAE.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 23- to 28-GHz 5-bit switch-type phase shifter with 1-bit calibration based on optimized ABCD matrix design methods for 5G MIMO system in 0.15-μm GaAs.
Int. J. Circuit Theory Appl., 2022

A 10-MHz to 50-GHz low-jitter multiphase clock generator for high-speed oscilloscope in 0.15-μm GaAs technology.
Int. J. Circuit Theory Appl., 2022

Promise Σ-protocol: How to Construct Efficient Threshold ECDSA from Encryptions Based on Class Groups.
IACR Cryptol. ePrint Arch., 2022

A 134-154 GHz Low-Noise Amplifier Achieving 36.3-dB Maximum Gain with 3.8-dB Minimum Noise Figure for D-Band Imaging System.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A Two-Way Current-Combining W-band Power Amplifier Achieving 17.4-dBm Output Power with 19.4% PAE in 65-nm Bulk CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

A 26-38GHz Ultra-Wideband Balanced Frequency Doubler in 0.15µ m GaAs pHEMT Process.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
A 5G Wireless Event-Driven Sensor Chip for Online Power-Line Disturbances Detecting Network in 0.25 μm GaAs Process.
IEEE Trans. Ind. Electron., 2021

A 120-150 GHz Power Amplifier in 28-nm CMOS Achieving 21.9-dB Gain and 11.8-dBm P<sub>sat</sub> for Sub-THz Imaging System.
IEEE Access, 2021

Analysis and Design of a 35-GHz Hybrid π-Network High-Gain Phase Shifter With 360° Continuous Phase Shifting.
IEEE Access, 2021

A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS.
IEEE Access, 2021

A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio.
Proceedings of the 47th ESSCIRC 2021, 2021

A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A C-Band Power Amplifier with Over-Neutralization Technique and Coupled-Line MCR Matching Methods for 5G Communication in 0.25-μm GaAs.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

An 4<sup>th</sup>-order N-path Bandpass Filter with a Tuning Range of 1-30 GHz and OOB Rejection > 30 dB in 28 nm CMOS.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

A 79GHz 5-bit Phase Shifter With π-Network in 28-nm CMOS.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

Promise $\varSigma $-Protocol: How to Construct Efficient Threshold ECDSA from Encryptions Based on Class Groups.
Proceedings of the Advances in Cryptology - ASIACRYPT 2021, 2021

2020
A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC.
IEEE Access, 2020

Analog Integrated Circuits Based on Wafer-Level Two-Dimensional MoS<sub>2</sub> Materials With Physical and SPICE Model.
IEEE Access, 2020

A Practical NIZK Argument for Confidential Transactions over Account-Model Blockchain.
Proceedings of the Provable and Practical Security - 14th International Conference, ProvSec 2020, Singapore, November 29, 2020

A 10-18 GHz GaN Power Amplifier Based on Asymmetric Magnetically Coupled Resonator.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019
A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 140 GHz, 4 dB Noise-Figure Low-Noise Amplifier Design with the Compensation of Parasitic Capacitance CGS.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Novel Nauta Transconductor for Ultra-Wideband gm-C Filter with Temperature Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 130-150 GHz Power Amplifier for Millimeter Wave Imaging in 65-nm CMOS.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A 256MHz Analog Baseband Chain with tunable Bandwidth and Gain for UWB Receivers.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

SPICE Modeling and Simulation of High-Performance Wafer-Scale MoS2 Transistors.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A 36-40 GHz VCO with bonding inductors for millimeter wave 5G Communication.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A 22-40.5 GHz UWB LNA Design in 0.15um GaAs.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
A 5-to-8-GHz Wideband Miniaturized Dielectric Spectroscopy Chip With $I/Q$ Mismatch Calibration in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2017
An Efficient NIZK Scheme for Privacy-Preserving Transactions over Account-Model Blockchain.
IACR Cryptol. ePrint Arch., 2017

A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2015
A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system.
Proceedings of the ESSCIRC Conference 2015, 2015

A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOS.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A 39 GHz-80 GHz millimeter-wave frequency doubler with low power consumption in 65nm CMOS tehnology.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A wide-division-ratio 100MHz-to-5GHz multi-modulus divider chain for wide-band PLL.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
An overview of new design techniques for high performance CMOS millimeter-wave circuits.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 131.5GHz, -84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOS.
Proceedings of the ESSCIRC 2014, 2014

2013
A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-line.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
A low power programmable band-pass filter with novel pseudo-resistor for portable biopotential acquisition system.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012


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