Roshan Weerasekera
Orcid: 0000-0002-6287-2731
According to our database1,
Roshan Weerasekera
authored at least 26 papers
between 2004 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2023
Proceedings of the Fungal Machines - Sensing and Computing with Fungi, 2023
2019
2018
2015
BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC-TSI).
IEEE Des. Test, 2015
2013
High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks.
Proceedings of the NOCS 2011, 2011
Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Design exploration of 3D stacked non-volatile memory by conductive bridge based crossbar.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
3-D memory organization and performance analysis for multi-processor network-on-chip architecture.
Proceedings of the IEEE International Conference on 3D System Integration, 2009
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits.
Proceedings of the IEEE International Conference on 3D System Integration, 2009
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh.
Proceedings of the IEEE International Conference on 3D System Integration, 2009
2008
System Interconnection Design Trade-offs in Three-Dimensional (3-D) Integrated Circuits.
PhD thesis, 2008
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime.
IEEE Trans. Very Large Scale Integr. Syst., 2008
2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
2006
Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006
2005
Proceedings of the Integrated Circuit and System Design, 2005
2004
Proceedings of the 2004 International Symposium on System-on-Chip, 2004