Shunya Nagata

According to our database1, Shunya Nagata authored at least 2 papers between 2018 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018


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