Shunya Nagata

According to our database, Shunya Nagata authored at least 5 papers between 2018 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 3nm 0.167fJ/b 5.27Mb/mm² Configurable TCAM with Macro-Wise Pipelined Search Methods for Automotive Applications.

Shunya Nagata, Yohei Sawada, Kenichiro Takiguchi, Masao Morimoto, Shinji Tanaka, Naoya Fujita, Tomohiro Miura, Daisuke Nakamura, Takashi Ito

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2024

An Area-Efficient PVT-Dependent Adaptive Assist Termination Technique with SNM Detector for High Density SRAM.

Shunya Nagata, Daiki Kitagata, Kouji Satou, Daisuke Nakamura, Koji Tanaka, Miki Tanaka, Haruyuki Okuda, Kenichiro Takiguchi

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

22-nm Data Backup SRAM Using 3.3V IO MOSs with Ultralow-Voltage-Drop Erasure Technique for Secure IoT Applications.

Daiki Kitagata, Shunya Nagata, Kouji Satou, Daisuke Nakamura, Koji Tanaka, Miki Tanaka

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2019

A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU.

Yoshisato Yokoyama, Kenji Goto, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Yoshiki Tsujihashi, Yuichiro Ishii

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018

40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications.

Yoshisato Yokoyama, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Makoto Yabuuchi, Yuichiro Ishii, Koji Nii

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018