Yoshisato Yokoyama

According to our database, Yoshisato Yokoyama authored at least 10 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture.

Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing.

Yoshisato Yokoyama, Koji Nii, Yuichiro Ishii, Shinji Tanaka, Kazutoshi Kobayashi

IEEE J. Solid State Circuits, 2023

2021

Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs.

Yoshisato Yokoyama, Yuichiro Ishii, Koji Nii, Kazutoshi Kobayashi

IEEE Trans. Very Large Scale Integr. Syst., 2021

2020

A 29.2 Mb/mm² Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit.

Yoshisato Yokoyama, Miki Tanaka, Koji Tanaka, Masao Morimoto, Makoto Yabuuchi, Yuichiro Ishii, Shinji Tanaka

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019

A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU.

Yoshisato Yokoyama, Kenji Goto, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Yoshiki Tsujihashi, Yuichiro Ishii

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018

40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications.

Yoshisato Yokoyama, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Makoto Yabuuchi, Yuichiro Ishii, Koji Nii

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017

A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode.

Yoshisato Yokoyama, Yuichiro Ishii, Haruyuki Okuda, Koji Nii

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2015

A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU.

Yoshisato Yokoyama, Yuichiro Ishii, Toshihiro Inada, Koji Tanaka, Miki Tanaka, Yoshiki Tsujihashi, Koji Nii

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU.

Yoshisato Yokoyama, Yuichiro Ishii, Hidemitsu Kojima, Atsushi Miyanishi, Yoshiki Tsujihashi, Shinobu Asayama, Kazutoshi Shiba, Koji Tanaka, Tatsuya Fukuda, Koji Nii, Kazumasa Yanagisawa

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues.

Yoshisato Yokoyama, Yuichiro Ishii, Koji Tanaka, Tatsuya Fukuda, Yoshiki Tsujihashi, Atsushi Miyanishi, Shinobu Asayama, Keiichi Maekawa, Kazutoshi Shiba, Koji Nii

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014