Yuichiro Ishii

According to our database1, Yuichiro Ishii authored at least 18 papers between 2007 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A 29.2 Mb/mm<sup>2</sup> Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
Decomposition of Movement Data of Quadruped Robot by Using Autoencoder.
Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2018

Development of the experimental system that can acquire the gait data online in a quadruped robot.
Proceedings of the International Symposium on Micro-NanoMechatronics and Human Science, 2018

40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A 6.05-Mb/mm<sup>2</sup> 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 5.92-Mb/mm<sup>2</sup> 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline.
Proceedings of the Symposium on VLSI Circuits, 2014

40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry.
Proceedings of the International Symposium on Quality Electronic Design, 2013

2012
A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues.
IEEE J. Solid State Circuits, 2011

Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2007
Multilingual phrase-based concordance generation in real-time.
Inf. Retr., 2007


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